In organic flip chip packages, there exists a significant difference in the Coefficient of Thermal Expansion (CTE) between an Integrated Circuit (IC) chip and the organic substrate to which it is interconnected by means of small solder joints, which may be generally referred to as Controlled Chip Collapse Columns (C4s). This mismatch in CTE imposes large strains on the C4s and/or the underlying circuitry of the IC chip, thereby compromising yield (e.g. failure during temperature excursions such as solder reflow for the C4 interconnections) and reliability (e.g. failure during application temperature excursions). This fundamental issue has been somewhat mitigated by the use of underfill materials in the gap between the IC chip, the organic substrate, and the C4s. The underfill material provides reinforcement to the inherent fatigue resistance of the C4s. One drawback of this mitigation approach is that the underfill material, once cured, polymerized, and adhesively bonded to the C4s, IC chip, and substrate, limits the lateral (X-Y) contraction of the substrate during the cool down cycle of underfill cure, thereby causing: (1) the substrate to deform in the Z-direction (warpage); and (2) high residual stresses between the underfill and the IC chip, especially at the IC corners where the Distance to Neutral Point (DNP) (i.e., center point of the IC chip) is highest. These issues are exacerbated with higher densities (i.e., smaller C4s), larger chips (i.e., higher DNPs) and less compliant C4 materials (such as certain Pb-free solders), all of which are current trends in micro-electronic packaging. Moreover, if the underfill is not present during initial joining of the IC chip to the substrate, then no such protection is afforded at this stage.
Solutions have been offered and/or developed to further mitigate the above CTE mismatch and/or further improve upon the underfill solution. For example, certain underfills exist that may be applied prior to the formation of the C4 joints between the IC chip and the organic substrate, such as wafer level underfills and “No Flow” underfills. However, drawbacks to these solutions include increased difficulties in affecting the initial C4 joints and compromised reliability attributes. Many underfill formulations have been and continue to be developed in an effort to reduce the aforementioned warpage and stress effects, but there is usually a trade-off in either the protection afforded the C4s or the protection afforded the underlying IC chip circuitry. Other solutions relate to maintaining a Z-direction force during certain aspects of package assembly such as when the heat spreader is attached. While providing improved resistance against warpage, such a process increases assembly cost and imparts greater stresses to other interfaces.
Another issue with the aforementioned trends in micro-electronic packaging, and specifically involving higher densities and larger IC chips, is that organic substrates are becoming less co-planar due to increased warping prior to any C4 joining to the IC chip. Furthermore, some advances in organic substrate development intended to increase electrical performance have introduced new substrate structures that tend to be less co-planar. However, the greater the amount of warpage, the more difficult it becomes to effect 100% joining efficiency of all C4 interconnections between the IC chip and the substrate. This is especially true when using smaller C4 interconnection structures, which include smaller C4 solder bumps on the IC chip and smaller solder receiving pads on the organic substrate.
Based on the foregoing, there exists a need for an improved system and method for reducing stress and warpage in flip chip packages.